1. Field of the Invention
Implementations consistent with the principles of the invention relate generally to data communication and, more particularly, to the use of a scalable central memory switching fabric architecture within a data transfer device.
2. Description of Related Art
A typical shared memory switching architecture includes input and output ports connected via a shared memory switching fabric. Typically, a shared memory switching architecture is used only when the desired aggregate system bandwidth can be achieved using a memory data width equal to or less than a cell size (for cell systems) or a minimum packet size (for packet systems). The shared memory switch architecture sometimes includes multiple memory subsystems. In this case, statistical or hash-based load balancing may be used between the memory subsystems. These approaches can be blocking and/or slower than wire speed.
For high bandwidth systems, lightly buffered or unbuffered cross-point architectures are typically used. These architectures often include delay-bandwidth buffer memory at the ingress and egress line cards. As a result, the memory bandwidth of the system is reduced to that of the line card instead of that of the entire system. With the cross-point architecture, each packet is written and read twice at each of the line cards. Therefore, the total system memory bandwidth required is double that of a shared memory switching architecture. Further, cross-point architectures typically have significant blocking characteristics on a port-to-port basis when there are many sub-ports (streams) per line card.